1. Field of the Invention
The present invention relates to microelectronic device fabrication, and more particularly, to a method and system for adjusting semiconductor wafer fabrication equipment so as to improve temperature control and process uniformity.
2. Description of the Related Technology
Thermal processing of semiconductors is a powerful technique for fabrication of ultra-large-scale integrated (ULSI) electronic devices. Numerous silicon fabrication technologies use thermal processing techniques, including thermal oxidation, nitridation, dopant diffusion, epitaxy and thermal annealing. Refractory metal silicide formation and chemical vapor deposition (CVD) are other significant silicon device fabrication processes that benefit from thermal reactors. For example, CVD is useful in the formation of dielectric oxides and nitrides in addition to amorphous silicon and polysilicon, as well as conductors, such as aluminum, copper, tungsten, and titanium nitride.
A thermal reactor common in the art employs two banks of heating lamps arranged in orthogonal or crossed directions above and below a susceptor holding a semiconductor wafer. Each surface of the semiconductor wafer faces one of the two banks of heating lamps. A controller within the thermal reactor adjusts relative power to each lamp to maintain a desired temperature during wafer processing. The controller receives signals indicative of wafer temperatures from temperature probes, such as a set of pyrometers or thermocouples. The controller uses these temperature signals to make adjustments to the heating lamps to ensure a uniform temperature across the wafer surface.
To place the reactor in an operating condition, the heating lamps require various adjustments prior to wafer processing. For example, one may need to adjust the position of the heating lamps as well as their orientation relative to a wafer in the chamber. Similarly, each temperature sensor, such as a pyrometer or thermocouple, generally requires a controller set point adjustment to account for variances in the sensitivity and accuracy of each sensor, as well as their position relative to the wafer. While some efforts have been made to measure thickness to make these adjustments as described by Shaper et al. in J. Electrochem. Soc., 143, 374 (1996), such efforts are cumbersome, time-consuming and complicated requiring numerous thickness measurements, optimization studies and curve fitting. Currently, these adjustments to place the thermal reactor in an operating condition are very tedious and costly to make. For example, in a thermal reactor used for silicon epitaxy, crystal structure defects, such as slip planes, dislocations and stacking faults, may result from temperature variations across the wafer surface. These defects are the only evidence available to a maintenance technician to identify and make wafer heating changes to eliminate the defects. However, the defects provide no indication as to the location or the magnitude of surface temperature variations caused by the heating lamps.
Thus, equipment maintenance technicians employ a trial and error process to make the necessary adjustments to minimize surface temperature differences. For example, a slip plane defect in a silicon epitaxy layer appears as a line when viewed on an interference/contrast microscope using 50X magnification. The maintenance technician inspects the defective wafer to identify the slip plane defects and their locations to make adjustments. After completing the adjustments, the maintenance technician processes another production wafer to surmise the effectiveness of the adjustments. In all likelihood, this production wafer includes different slip plane defects. Thus, the maintenance technician makes additional adjustments to compensate for the different slip plane defects and continues this iterative trial and error process until no defects result after processing a production wafer. The inherent inefficiency of the trial and error method causes the semiconductor manufacturer to lose valuable production time as well as production wafers.
Maintenance technicians may also use an instrumented wafer to determine changes needed to minimize surface temperature variation. An instrumented wafer is a standard silicon wafer having a plurality of thermocouples mounted through its top surface. Each thermocouple provides signals indicative of the wafer temperature at its mounting location through metal wires connected to a data acquisition device. To use the instrumented wafer, a thermal reactor must be configured to receive the thermocouples and their associated metal wiring. Wafer processing conditions are then simulated in the thermal reactor while the plurality of thermocouples provide signals indicative of the wafer surface temperature profile to a data acquisition device for later analysis. A maintenance technician then analyzes the temperature profile data from the data acquisition device to determine changes needed to minimize surface temperature variations.
Unfortunately, the instrumented wafer thermocouples routinely fail after one to two hours of use under standard wafer processing conditions. Similarly, the thermocouples often provide false readings under the hydrogen flows of standard wafer processing conditions. In addition, the presence of the metal wiring associated with the instrumented wafer thermocouples creates an unacceptable risk of contamination to many semiconductor manufacturers. Other semiconductor manufacturers require a thermal reactor reconstruction or chamber clean after any use of the instrumented wafer. Moreover, frequent thermocouple failures and false thermocouple readings decrease the reliability of the temperature data acquired and thus the effectiveness of any adjustments made in response to this temperature data. Lastly, use of the instrumented wafer incurs substantial costs to procure an instrumented wafer, to reconfigure the thermal reactor to receive an instrumented wafer and to obtain and analyze the instrumented wafer data.
Furthermore, thermal reactors often require routine preventive maintenance to ensure repeatable and reliable performance. In some cases, the preventive maintenance operations occur as frequently as once per week. This causes a significant amount of down time whereby a semiconductor manufacturer loses productivity of the reactor during the maintenance operation. To compound the loss of productivity, the reactors often require adjustments to the lamps and temperature sensors to return the reactor to operating condition after maintenance operations. As discussed above, these adjustments are tedious, time consuming and costly. To ensure efficient, cost-effective fabrication of microelectronic devices, semiconductor manufacturers require a simple and effective method to place their thermal reactors in operating condition after installation and routine preventive maintenance operations.